Improved signal traceability throughout the design flow via the graphical user interface (GUI) to help designers trace a signal between the HDL source to the RTL view, and to the technology view and back again. The SERDES analysis tools in Radiant 3.0 have been enhanced to accommodate the higher SERDES bandwidths supported by CertusPro-NX devices. New feature upgrades available in Radiant 3.0 include: For experienced FPGA developers, Lattice Radiant 3.0 allows for more granular control over FPGA settings if specific optimizations are required.” “Developers with little to no experience working with FPGAs can quickly leverage the automated features of Lattice Radiant.
“Lattice Radiant 3.0 design software gives developers an easy-to-follow user experience the tool leads them through the steps of the development flow, including design creation, importing IP, implementation, bitstream generation, downloading the bitstream onto an FPGA, and debugging,” said Roger Do, Senior Product Line Manager, Software at Lattice Semiconductor. “The Lattice Radiant tool has a modern user interface that is highly intuitive and very easy to use, which reduces design complexity and helps us get products to market faster.” “As a leading provider of FPGA-based SoM solutions for the industrial and automotive markets, we have decades of experience working with various software tools used in hardware development,” said Antti Lukats, CTO, Trenz Electronic GmbH. They also evaluate the design software used to configure the hardware for its ease of use and supported features, as those characteristics can have a significant impact on overall system development time and cost. When system developers evaluate hardware platforms, the actual hardware is only a part of their selection criteria. The tool supports higher density devices like the new Lattice CertusPro™-NX family – the latest family based on the Lattice Nexus™ platform – and offers new features that make it faster and easier than ever to develop Lattice FPGA-based designs. Overall, new Radiant 3.0 features reduce runtime by 15% while delivering a 7% increase in design performance.HILLSBORO, Ore.-( BUSINESS WIRE)- Lattice Semiconductor Corporation (NASDAQ: LSCC), the low power programmable leader, today announced availability of the latest version of its popular software design tool for use with low power Lattice FPGAs, Lattice Radiant® 3.0. Timing analysis now runs independently of other operations, providing significant speed benefits and improving an iterative design process-changes need only run timing analysis, mapping, and place-and-route when required. The same timing constraints and timing analysis are utilized by both.
This version of Radiant supports two synthesis engines: the Lattice Synthesis Engine (LSE) and the Synplify Pro synthesis engine. Other enhancements in this new version include better signal traceability throughout the design flow, with graphical feedback showing signal traces between the HDL source and RTL view.
SERDES analysis has been enhanced so that the chip can handle the higher-bandwidth SERDES. Software support for the CertusPro-NX includes the new Radiant 3.0 development tool. The smallest package limits the number of SERDES and I/O but not the number of logic cells (Fig. Their soft error rate is significantly better than the competition. Lattice targets rugged and safety-critical applications with these FPGAs-the chips have an operating temperature range from −40 to 125☌. Likewise, the DSP support has been enhanced to work with machine-learning (ML) applications. Large amounts of on-chip memory are included to meet the changing needs of designers.
The chips also support LPDDR4 external memory. The FPGAs feature large and small internal memory blocks designed for low-latency operation.